`timescale 1 ns / 1 ps

// `include "psmbaby.v"
`include "meu.v"

module top(
    input clk , 
    output reg [0:0]led 
); 

/*---------------------------- mcu nets --------------------------*/

reg  rst_n ;
reg [2:0] rst_cnt = 0  ;
always @(posedge clk ) begin;
    rst_cnt <= &rst_cnt ? rst_cnt : rst_cnt + 1'b1;
    rst_n <= &rst_cnt;
end

wire [7:0] o_port , o_portid ;
wire o_wen ;

meu #(
    .ROM_FILE ("firmware.hex"),
    .ROM_NUM (128),
    .RAM_SIZE (32)
) u_eu (
    .clk(clk),
    .rst_n(rst_n),

    .o_wen(o_wen),
    .o_portid(o_portid),
    .o_port(o_port),
    .i_port()
);


always @(posedge clk ) begin
    if(o_wen)begin
        if(o_portid == 8'h0 )led <= o_port[0];
    end
end



endmodule
